Organization Name：
（组织名称） Teradyne
（组织名称） Teradyne
Organizational Unit：
（组织单位） Semiconductor Test Division, Logic Design
（组织单位） Semiconductor Test Division, Logic Design
Maturity Level：
（成熟度） Maturity Level 3
（成熟度） Maturity Level 3
Appraisal End Date：
（评估结束日期） Jun 18, 2015
（评估结束日期） Jun 18, 2015
Lead Appraiser：
（主任评估师） Patrick O'Toole
（主任评估师） Patrick O'Toole
Sponsor：
（发起人） Richard Burns
（发起人） Richard Burns
- Sampling Summary：
（抽样汇总） -
Sampling Factors: Location (Not Relevant: Although some work is performed in California and Oregon, the primary work is performed and managed from North Reading, MA. Everyone, regardless of location, follows the same Logic Design processes.)
Customer (Not Relevant: All Logic Design projects are being conducted for internal customers.)
Size (Not Relevant: Although the size of the CHIP has an influence on the complexity of the projects, they all follow the same set of processes. We will be evaluating a LARGE project to ensure we get the most robust view of how the work is performed.)
Organizational Structure (Not Relevant: The current appraisal is limited to a single function – the Logic Design group.)
Type of Work (Not Relevant: The type of work performed by the Logic Design group is reasonably consistent and does not affect the processes used to perform the work.)
Pseudo Factor: This factor is being established to meet the SAS requirement that there must be at least one relevant sampling factor.Sampling Factor Values: All Projects (Pseudo Factor): This value is only being added to accommodate SAS limitations.
No projects (Pseudo Factor): This value is only being added to accommodate SAS limitations.Subgroups: All Projects: This subgroup is only being added to accommodate SAS limitations.
41 People, 8 Basic Units
– All Projects
说明：该信息摘自CMMI官网公示，更多详情请点击这里查看。注：CMMI认证有效期3年，过期链接失效。
